Capacitance multiplier circuits are known in the art. For example, U.S. Pat. No. 3,911,296, William F. Davis, which is assigned to Motorola, Inc. discloses such a circuit. This prior art capacitance multiplier circuit comprises an integrated capacitor structure coupled between the collector and base electrodes of an integrated NPN transistor. As brought out in this prior art patent, the effective capacitance is a function of the amplification factor, beta, of the device.
Although the prior art circuit is quite useful for multiplying either an "on-chip" capacitance or discrete capacitance value by the amplification factor of the transistor to produce a large effective capacitance at the collector of the NPN transistor, the prior art circuit suffers from several disadvantages. The most significant disadvantage of the prior art circuit is that the resultant effective capacitance of the beta multiplied capacitor is a function of the beta of the transistor and is therefore process and temperature dependent. Thus, due to process and temperature variations the value of the effective capacitance will vary between a minimum and maximum limit which may not be acceptable in a system utilizing such a capacitance multiplier circuit.
Although the prior art capacitance circuit utilizes small "on-chip" value capacitor, another disadvantage is that this capacitor takes up die area of the integrated circuit chip. In some applications, i.e., large scaled integrated circuits, the useable area of the integrated circuit chip becomes quite important such that elimination of the need to assign a portion of the area to fabricate "on-chip" capacitors can be a significant advantage to the circuit designer.
Thus, a need exists for providing a capacitance multiplier circuit for deriving large effective capacitance values which are neither process or temperature dependent while simultaneously reducing the "on-chip" area required to produce the effective capacitances.